Low-power CMOS fully-folding ADC with a novel bit synchronization architecture

A 6-bit 250MHz low-power CMOS fully-folding analog-to-digital converter is designed in a 0.5??m standard digital CMOS process. Folding circuits are not only used in fine converter but also in coarse one. A novel bit synchronization architecture also based on folding circuits is presented to reduce the number of comparators for bit synchronization and simplify the logic design. The total power dissipation is 34mW at a 5V supply. ?2006 IEEE.EI