A 16-bit 312.5-kHz Bandwidth Fourth-order One-Bit Switched-Capacitor Sigma-Delta Modulator

In this paper, a high-resolution medium-frequency single-loop fourth-order 1-bit sigma-delta modulator is implemented in 0.18 mu m CMOS technology. The modulator has been presented with an oversampling ratio of 50, clock frequency of 31.25MHz, 312.5 kHz bandwidth, and achieves a peak SNR of 101.7dB, which is 16.6-bit resolution, 103dB dynamic range. The whole circuits consume 58.55-mW from a single 1.8V supply voltage. The experimental results show a figure-of-merit (FOM) of 170.27dB. A system to circuit level design is finished in this paper.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000289818000043&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a60747a720701Engineering, Electrical & ElectronicEICPCI-S(ISTP)