A Parallel Intra Prediction Architecture for H.264 Video Decoding

In this paper, an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 video coding standard is adopted. The hardware design is based on a novel organization of the intra prediction equations. Compared with conventional architecture, infra predict efficiency is enhanced. The Verilog RTL is verified to work at 103 MHz in a Xilinx II FPGA(1).Engineering, Electrical & ElectronicEICPCI-S(ISTP)