A self-aligned, electrically separable double-gate MOS transistor technology for dynamic threshold voltage application

Zhang, SD
Lin, XN
Huang, R
Han, RQ
Chan, MS

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Publication date

January 2003

DOI

10.1109/TEd.2003.818598

Publisher

ieee电子器件汇刊

ISSN

0018-9383

Journal

0018-9383

Abstract

In this brief, a self-aligned electrically separable double-gate (SA ESDG) MOS transistor technology is proposed and demonstrated. The SA ESDG structure is implemented by defining a dummy top gate that is self-aligned to the bottom gate and then later replacing the dummy using a real top gate. The proposed process is applied to the single-grain Si film formed by recrystallizing a low-pressure chemical vapor deposition a-Si with a metal induced unilateral crystallization technique and enhancing the grain sizes in a subsequent high temperature annealing step. The ideal device structure resulting form the process is verified by scanning electron microscope imaging. The good current-voltage characteristics and the noticeable dynamic threshold v...