The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB-MOSFET). The characteristics of the 45 nun and the 20 nun n-channel ASB-MOSFETs, which adopt a Schottky barrier height of 0.9 eV at source and that of 0.2 eV at drain, have been simulated and discussed by the comparisons with the conventional Schottky Barrier MOSFETs (SB-MOSFET). With a higher lon/1off ratio, the ASB-MOSFET structure has shown a better performance than the conventional SB-MOSFETs. (c) 2005 Elsevier Ltd. All rights reserved.http://gateway.webofknowledge.com/gateway/Gateway.cgi?GWVersion=2&SrcApp=PARTNER_APP&SrcAuth=LinksAMR&KeyUT=WOS:000236070300010&DestLinkType=FullRecord&DestApp=ALL_WOS&UsrCustomerID=8e1609b174ce4e31116a607...
A novel n-channel Schottky barrier MOSFET with dual-layer silicide source/drain (DS-SB-MOSFET) has b...
A self-assembly patterning method for generation of epitaxial CoSi 2 nanostructures was used to fabr...
In the present work, we have systematically investigated the design of Asymmetric SPAcer-layer Tunne...
An n-channel planar asymmetric Schottky barrier source/drain MOSFET (ASB), in which the source-side ...
Abstract—A novel asymmetric MOSFET with no lightly doped drain on the source side is simulated on bu...
The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/dr...
In the letter, a new Schottky-barrier double-gate n-metal-oxide-semiconductor field effect transisto...
In the letter, a new Schottky-barrier double-gate n-metal-oxide-semiconductor field effect transisto...
Ideal MOSFET is intrinsically symmetrical in source and drain, and all existing models describing MO...
A novel structure of Schottky Barrier MOSFET is demonstrated. The devices are designed upon the conc...
Schottky barrier tunnelling transistors with gate length of 70 nm have been fabricated using spacer ...
A complete description of physical models for fabricated Asymmetric Spacer Tunnel Layer (ASPAT) diod...
Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are sim...
A self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabri...
A novel field effect transistor (FET), asymmetric gate (AG) FET, is proposed and its excellent perfo...
A novel n-channel Schottky barrier MOSFET with dual-layer silicide source/drain (DS-SB-MOSFET) has b...
A self-assembly patterning method for generation of epitaxial CoSi 2 nanostructures was used to fabr...
In the present work, we have systematically investigated the design of Asymmetric SPAcer-layer Tunne...
An n-channel planar asymmetric Schottky barrier source/drain MOSFET (ASB), in which the source-side ...
Abstract—A novel asymmetric MOSFET with no lightly doped drain on the source side is simulated on bu...
The performance of the n-channel Schottky barrier MOSFET with asymmetric barrier height at source/dr...
In the letter, a new Schottky-barrier double-gate n-metal-oxide-semiconductor field effect transisto...
In the letter, a new Schottky-barrier double-gate n-metal-oxide-semiconductor field effect transisto...
Ideal MOSFET is intrinsically symmetrical in source and drain, and all existing models describing MO...
A novel structure of Schottky Barrier MOSFET is demonstrated. The devices are designed upon the conc...
Schottky barrier tunnelling transistors with gate length of 70 nm have been fabricated using spacer ...
A complete description of physical models for fabricated Asymmetric Spacer Tunnel Layer (ASPAT) diod...
Double gate SBFET with asymmetric barrier heights at source/drain and the symmetric DG-SBFET are sim...
A self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabri...
A novel field effect transistor (FET), asymmetric gate (AG) FET, is proposed and its excellent perfo...
A novel n-channel Schottky barrier MOSFET with dual-layer silicide source/drain (DS-SB-MOSFET) has b...
A self-assembly patterning method for generation of epitaxial CoSi 2 nanostructures was used to fabr...
In the present work, we have systematically investigated the design of Asymmetric SPAcer-layer Tunne...