In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studied and compared with that of a conventional single-gate TFT. The double-gate TFT is predicted to suffer from a more severe anomalous off-current than the single-gate TFT. A smart double-gate TFT technology is proposed to decrease the off-current. The unique feature of the technology is the lithography independent formation of the self-aligned double-gate and the symmetric lightly doped drain (LDD) structures. With the LDD applied, the anomalous off-current of the fabricated double-gate TFT is reduced by three orders of magnitude from the range of 10(-9) A/mum to 10(-12) A/mum. The orVoff current ratio is increased by three orders of magnitude ...
This paper proposes a numerical simulation of the dual-gate organic thin film transistors (DG-OTFTs)...
Background: Power reduction is a serious design concern for submicron logic circuits, which can be a...
The Silicon-on-Insulator (SOI) technology allows the fabrication of devices with reduced parasitic c...
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studie...
In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demon...
In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) tech...
The electric characteristics of field-induced drain (FID) poly-Si thin-film transistors (poly-Si TFT...
In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is pro...
A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is pro...
In this paper, a novel self-aligned double-gate (SLambdaDG) TFT technology is proposed and experimen...
A double-gate (DG) a-IGZO TFT with separate bottom-gate and top-gate is fabricated and electrically ...
A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is pro...
A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is pro...
© 2015 Society for Information Display. We report a dual-gate (DG) self-aligned (SA) a-IGZO TFT pro...
Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-po...
This paper proposes a numerical simulation of the dual-gate organic thin film transistors (DG-OTFTs)...
Background: Power reduction is a serious design concern for submicron logic circuits, which can be a...
The Silicon-on-Insulator (SOI) technology allows the fabrication of devices with reduced parasitic c...
In this brief, the lateral electric field distribution in the channel of a double-gate TFT is studie...
In this paper, a self-aligned double-gate (SADG) TFT technology is proposed and experimentally demon...
In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) tech...
The electric characteristics of field-induced drain (FID) poly-Si thin-film transistors (poly-Si TFT...
In this letter, a novel self-aligned double-gate (SADG) thin-film transistor (TFT) technology is pro...
A lithography independent self-aligned bottom gate thin film transistor (SABG-TFT) technology is pro...
In this paper, a novel self-aligned double-gate (SLambdaDG) TFT technology is proposed and experimen...
A double-gate (DG) a-IGZO TFT with separate bottom-gate and top-gate is fabricated and electrically ...
A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is pro...
A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is pro...
© 2015 Society for Information Display. We report a dual-gate (DG) self-aligned (SA) a-IGZO TFT pro...
Recently, tunnel field-effect transistors (TFETs) have been regarded as next-generation ultra-low-po...
This paper proposes a numerical simulation of the dual-gate organic thin film transistors (DG-OTFTs)...
Background: Power reduction is a serious design concern for submicron logic circuits, which can be a...
The Silicon-on-Insulator (SOI) technology allows the fabrication of devices with reduced parasitic c...