Modeling Region Granularity of the D2M Memory SystemPin Tool driven test for the Split CacheHierarchy

Cache simulation is a potentially complex and time consuming task in the field of computer architecture. Often, only parts of a program are simulated due to practical time constraints. This thesis proposes a way to simulate entire benchmark programs using the Intel Pin platform (PIN) for research into the Directto-Master memory system (D2M). D2M is a design at the forefront of the computer architecture research field, but the granularity of cacheline group sizes has not been fully investigated. We run tests on ten benchmarks from the PARSEC 3.0 suite and five benchmarks from the SPEC CPU 2006 suite to investigate the effects of different cacheline size groupings, known as region size, in D2M. For each benchmark, a set of statistics are generated for each region size tested. We analyze these results to show the effects of region size on the D2M design. Specifically we analyze the effects of region size on the metadata (MD) hierarchy, which is the structure responsible for tracking cache lines in the data hierarchy. Ten out of fifteen applications have peak MD1 traffic with a region size of 16 or 32 cachelines. These applications, however, are also least effected by change in region size. The applications that are most effected by region size are the ones that have peak first level MD (MD1) traffic with either smaller or larger regions. When considering overall MD traffic, the region size of 64 cachelines generates the most overall MD traffic and the lowest number of cache misses. This is because of lower overhead in the MD hierarchy which translates to extended MD reach. In this way, we model and simulate D2M using PIN to generate statistics about the different D2M region sizes. These results can be taken into consideration when running more in-depth simulations which could potentially save researchers time when performing cache simulation