Add to ORKGA method for reducing circuit sensitivity to single event upsets in programmable logic devices, involves identifying single event upset sensitive gates within a single event upset sensitive sub-circuit of a programmable logic device as determined by the input environment and introducing triple modular redundancy and voter circuits for each single event upset sensitive sub-circuit so identified
With the increasing demand for more durable products, the necessity of designing more resilient prod...
This thesis presents a redundancy identification (RI) method, namely, the Improved Structure Based (...
The circuit concept of programmable logic gates based on the controlled quenching of series-connecte...
A method for reducing circuit sensitivity to single event upsets in programmable logic devices, invo...
The present invention includes a circuit-level system and method for preventing the propagation of s...
We present a design technique, called partial evaluation triple modular redundancy for hardening com...
Due to the character of the original source materials and the nature of batch digitization, quality ...
2012-05-01Reduced scaling of feature sizes and process variations in CMOS nano-technologies introduc...
University of Minnesota Ph.D. dissertation. December 2009. Major: Electrical Engineering. Advisor: D...
In this work we are going to simulate a field programmable cyclic redundancy check circuit architect...
Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in different parts to imp...
Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware re...
The topic of this thesis are methods for power reduction in digital circuits by reducing average swi...
The area of fault-handling in reconfigurable logic devices is one that continues to receive research...
This thesis focuses on fault tolerance which is kind of dependable computing implementation. It deal...
With the increasing demand for more durable products, the necessity of designing more resilient prod...
This thesis presents a redundancy identification (RI) method, namely, the Improved Structure Based (...
The circuit concept of programmable logic gates based on the controlled quenching of series-connecte...
A method for reducing circuit sensitivity to single event upsets in programmable logic devices, invo...
The present invention includes a circuit-level system and method for preventing the propagation of s...
We present a design technique, called partial evaluation triple modular redundancy for hardening com...
Due to the character of the original source materials and the nature of batch digitization, quality ...
2012-05-01Reduced scaling of feature sizes and process variations in CMOS nano-technologies introduc...
University of Minnesota Ph.D. dissertation. December 2009. Major: Electrical Engineering. Advisor: D...
In this work we are going to simulate a field programmable cyclic redundancy check circuit architect...
Multiple upsets would be available in SRAM-based FPGAs which utilizes SRAM in different parts to imp...
Technology scaling poses an increasing challenge to the reliability of digital circuits. Hardware re...
The topic of this thesis are methods for power reduction in digital circuits by reducing average swi...
The area of fault-handling in reconfigurable logic devices is one that continues to receive research...
This thesis focuses on fault tolerance which is kind of dependable computing implementation. It deal...
With the increasing demand for more durable products, the necessity of designing more resilient prod...
This thesis presents a redundancy identification (RI) method, namely, the Improved Structure Based (...
The circuit concept of programmable logic gates based on the controlled quenching of series-connecte...