Analysis and test of the effects of single event upsets affecting the configuration memory of SRAM-based FPGAs

In the Ph.D. thesis1 from which this summary has been extracted the author proposed a framework of methodologies for the analysis and test of the effects of Single Event Upsets (SEUs) in the configuration memory of SRAM-based FPGA systems. In particular, an accurate SEU simulator for the early assessment of the sensitivity of SRAM-based FPGA systems to SEUs has been proposed, as well as a model-checking based untestability analysis methodology and a genetic algorithm-based automatic test pattern generation environment. All the proposed methodologies have been applied to a set of circuits from the ITC'99 benchmark and the SEU simulator has also been applied to the MiniMips microprocessor