Reconfiguration Control Networks for FPGA-based Space Applications

Space processing applications deployed on SRAM-based Field Programmable Gate Arrays (FPGAs) are vulnerable to radiation-induced Single Event Upsets (SEUs). To efficiently mitigate configuration memory upsets, Triple Modular Redundancy (TMR) with Module-based Error Recovery (MER) has been proposed. TMR-MER systems rely on a Reconfiguration Control Network (RCN) to aggregate reconfiguration requests from voters that are distributed across the device to a central Reconfiguration Controller (RC), which performs partial reconfiguration on an affected module. This thesis focuses on the choice and impact of these RCNs on the system's reliability and performance. This thesis evaluates the suitability, utilization and performance of a token ring network in fulfilling the requirements of an RCN as the number of network connections is increased. As RCNs are not limited to a ring, we then carry out a comprehensive study and comparison of four possible RCN topologies, namely, a star, a bus, a token ring and an ICAP-based readback approach, with respect to their utilization, latency and SEU sensitivity as the network capacity increases. We evaluate these networks by implementing them on synthetic layouts as well as an experimental payload based on a Xilinx Artix-7 device and by injecting faults into these implementations. We show that of the RCN topologies studied, the ICAP-based approach is the most reliable, despite having the highest latency, while the star network also proves to be a strong contender due to its high performance. In our study, we found the reliability of TMR-MER to be significantly less than that of TMR-S unless the RCN was also triplicated and recovered. To more effectively localize errors in RCNs or other triplicated sub-components, this thesis proposes a fine-grained module error recovery scheme that without additional system hardware can localize and correct errors that classic MER fails to identify. We evaluate our proposal via a fault-injection campaign on a Xilinx Artix-7 application circuit and compare the reliability, the recovery latency and the energy cost of repairing errors, of our proposed method with those of a conventional MER approach and with periodic and on-demand blind scrubbing. We find the reliability of our proposal to be the highest and the energy expenditure to be the lowest amongst those methods considered. The thesis concludes with directions for further study