Run-Time Reconfiguration of Homogeneous MPSoCs for use in Embedded Systems

Multi-processor-system-on-chips (MPSoCs) with different numbers of cores have become increasingly popular in embedded systems. One of the main challenges in MPSoC systems is the exponentially increasing expense of fabricating chips. Instead of fabricating chips for each application separately, the embedded system industry seeks for an MPSoC system that can be efficiently used in a multitude of applications to reduce fabrication cost. In this thesis, we discuss a homogeneous MPSoC platform, and propose a set of novel run-time reconfiguration methods on this platform to execute multiple applications simultaneously and achieve benefits (improve performance, or reduce power consumption and area cost).The first method (DRMA) allows cores in MPSoCs to be rapidly reconfigured to change data widths. We present a case study with four cores to showcase the flexibility and efficacy of DRMA. Results show that the prototype of DRMA is capable of working as four 32-bit cores, two 64-bit cores, a single 128-bit core, and can achieve up to 4.11$\times$ speed up.In the second method (ADAPT), we examine hardware/software pipelines, which are useful for streaming applications. ADAPT can quickly detect bottleneck stages and add idle cores to bottleneck stages to improve throughput. If there is no idle core, a shuffling of cores across stages will be performed to balance workloads and improve throughput. For a variety of applications, ADAPT takes less than 2 μs for a run-time adaptation, and achieves up to 2.1 × speed up, compared to a state-of-the-art method (which is modified and implemented in the same platform for a fair comparison). Results illustrate the applicability of ADAPT for fine-grained run-time management to achieve high throughputs in MPSoC systems.The third method (E-pipeline) considers the system-level resource utilisation and power consumption when an MPSoC system simultaneously executes multiple pipelines. We show how multiple pipelines with dynamic workload variation can be efficiently executed in such a situation, and discuss how the system can switch cores within a pipeline (intra-elasticity) and across pipelines (inter-elasticity). Compared to the reference design method with clock gating, E-pipeline maintains the same power savings, and reduces core usages by an average of 37.7%