Reconfigurable high performance baseband towards software defined radio

The need to integrate multiple wireless communication protocols into a single low-cost, low power hardware platform is prompted by the increasing number of emerging communication protocols and applications in modern embedded systems. This thesis proposes an efficient methodology for integrating multiple wireless protocols in an ASIC which minimizes resource consumption. Two techniques are outlined in this thesis.First a hierarchical datapath merging algorithm is developed so that common components in two different communication circuits can be shared. The datapath merging approach builds a combined generic circuit with inserted multiplexers (MUXes) which can provide the same functionality of each individual circuit. The proposed method is orders of magnitude faster than circuits which emanated from existing datapath merging algorithms, and can switch communication protocols between packets with short switching time to create a virtual simultaneous multi-mode wireless communication.The second method shown in this thesis examines a more flexible reconfigurable method to support various baseband protocols. A pipelined programmable Software Defined Radio Coprocessor (SDR CP) is proposed which integrates multiple wireless communication baseband protocols. This coprocessor can dynamically select the suitable pipeline stages for each baseband protocol. The proposed coprocessor is flexible (compared to ASICs) and suitable for mobile application (compared to FPGAs and DSPs). A novel interface between the SDR CP and a general purpose processor is proposed. Any future protocol with signal processing, which is not supported in the SDR CP, can be executed on the general purpose processor, and the processed data can be fed back into the SDR CP stages efficiently. The area size of the coprocessor is smaller than an ASIC or FPGA implementation of multiple individual protocols, while the overheads of timing delay and power consumption are kept within reasonable levels. Additionally, fast protocol switching is supported.Each carefully designed stage in the SDR CP performs a certain signal processing function in a reconfigurable fashion.Firstly, a novel pipelined recursive architecture is proposed for reconfigurable linear feedback shift register (LFSR) based architecture, including the reconfigurable scrambler, convolutional encoder, and CRC circuits. High throughput in this architecture can be achieved by increasing parallelism. The area of this architecture is smaller than the combined ASIC implementation of multiple individual circuits, and power consumption is less than FPGA and ASIP/DSP processors.Secondly, a novel reconfigurable variable increment step (VIS) based interleaver is proposed for efficient multimode communication applications. The proposed reconfigurable interleaver supports both block and convolutional interleaving, costs little in area, consumes less power compared to other programmable solutions, and is sufficiently fast to satisfy even the most demanding of Software Defined Radio (SDR) applications. The proposed method is flexible (when compared to ASICs and some reconfigurable solutions) and suitable for mobile applications in terms of area, power consumption and throughput (when compared to FPGAs, processors and some other ASIC based reconfigurable proposals).Thirdly, the reconfigurable modulation mapping scheme is proposed in this thesis by an efficient tiny processor, named MAPro, which is programmable at runtime for differing modulation schemes. MAPro costs little in area, consumes less power compared to other programmable solutions, and is sufficiently fast to satisfy even the most demanding of Software Defined Radio (SDR) applications. The proposed method is flexible (when compared to ASICs) and suitable for mobile applications (when compared to FPGAs and ASIP processors). The area of MAPro is only 25\% of the combined ASIC implementation of multiple individual modulation mapping circuits, while the throughput meets specification. Power consumption is on average 110\% more than the ASIC implementation. However, MAPro outperforms both FPGA and ASIP processor significantly in area and power consumption. In terms of throughput, MAPro is similar to FPGA, and outperforms the ASIP/DSP processor.Next, a reconfigurable Viterbi decoder, which is an error correction circuit for the bits coded by the convolutional encoder, is proposed in this thesis. A limited number of Add-Compare-Select (ACS) units are used to update the new path metrics and select the most optimal trellis path. When the number of ACS is less than the number trellis state, ACS units work in a iteration fashion via a RAM to update the path metrics for all states. With a novel RAM address generator, different convolutional encoder coding rates and constraint lengths are supported.Lastly, a reconfigurable puncture, spreading and filter are developed based on the current literature, and embedded into the SDR CP to support the full baseband transmission and receiving paths.Wireless LAN (WLAN) 802.11a, 802.11b and Ultra Wide Band (UWB) full transmission chain, and certain function blocks from 802.11n, 802.11ac, WiMAX, WPAN, CDMA IS-95, LTE, DVB-T, ISDB-T and DTMB are developed and mapped to the proposed datapath merging methodology and the SDR CP to prove the efficacy of the author's proposal. The SDR CP has been extended to support the receiving chain as a complete SDR baseband solution