Energy-efficient low power optimisation methodologies for DRAM memory of embedded system

The increased demand on the long battery life of complex SoC systems requires power/energy aware methodologies and a comprehensive design process flow to optimise DRAM power/energy consumption of such power-hungry devices. For power/energy estimation purposes, a high level simulation approach is necessary due to the time consuming process of RTL/gate-level performance and power estimation. This thesis presents a design methodology with a seamless interface layer to glue the processor and memory component for building a system level processor-memory simulation framework. Over six mediabench benchmarks, our proposed simulator provides greater accuracy than trace-driven memory simulations which has shown an 80% variation on average in the choice of fixed memory latency in order to achieve the most accurate power consumption. Exploiting the last-level cache (LLC) is a well-known technique that reduces the DRAM memory traffic. The cycle-accurate simulation to accurately estimate the improved performance of a LLC configuration (especially for a large design space) is not a feasible option. This thesis introduces a technique to rapidly find out the system’s performance and energy consumption of the whole system while using different last-level cache configurations. Our methodology helps in significantly reducing the turnaround time to obtain the highly accurate execution time numbers (average absolute accuracy of 99.74% and 80.31% respectively for nine multimedia applications) with a significant reduction in the simulation time (from 257 days to 21 hours maximally). DRAM´s energy consumption is a very important component of total energy consumption of a system. Exploiting both the LLC and DRAM’s power modes together creates a chance of achieving the energy reduction in the DRAM system. Selecting a suitable LLC configuration for a target application to obtain the maximum energy savings takes a great amount of time. Thus, we developed a design framework and an energy reduction estimator to quickly explore a suitable configuration for maximum DRAM’s energy reduction. Our technique is able to predict the DRAM energy reduction for 330 LLC configurations in several days (with the accuracy within 4.4% on average) for 11 applications, whereas the cycle-accurate simulation took several months