Analyses and Optimisations for Pipelined MPSoCs

Heterogeneous MultiProcessor System on Chips (MPSoCs) are viable implementationplatforms for multimedia. However, optimisation of such platforms for performance,area footprint and energy consumption is a challenge. This thesis exploresthe paradigm of pipelined MPSoCs, and introduces design-time and run-time optimisations,in the form of an optimisation framework. This is the first time aframework has been proposed for optimisation of both the area footprint and energyconsumption of a pipelined MPSoC.In a pipelined MPSoC, processors are organised into pipeline stages and areconnected through First In First Out (FIFO) buffers. Application Specific Instructionset Processors (ASIPs) are used so that their customisation can be exploitedto optimise the area footprint of a pipelined MPSoC. Each processor has a numberof configurations, which are made up of differing custom instructions and cacheconfigurations, and thus enable performance-area trade-off.This thesis proposes analytical models and estimation methods to aid quickdesign space exploration of pipelined MPSoCs, when there are billions of designpoints. Three analytical models are proposed to estimate the execution time, latencyand throughput of a pipelined MPSoC, and two estimation methods are proposedto reduce the number of slow, full-system, cycle-accurate simulations. Researchershave used absolute accuracy and graphical fidelity to evaluate estimation models.Since there does not exist any metric to quantify fidelity, this thesis also proposesfidelity metrics to enable evaluation of estimation models in terms of not only theabsolute accuracy, but also the fidelity.For design space exploration, two algorithms are proposed to select one configurationper processor so as to minimise the area footprint of a pipelined MPSoCunder a latency or a throughput constraint. Experiments with a number of pipelinedMPSoCs, executing JPEG encoder, JPEG decoder, MP3 encoder and H.264 encoderapplications, showed that the analytical models and the estimation methods had amaximum absolute error of 18.67% and a minimum fidelity of 0.88. The proposedanalytical models and estimation methods resulted in simulation times of only severalhours for design spaces containing up to 10^18 design points. The proposedexploration algorithms explored such large design spaces for Pareto fronts in lessthan seven minutes.Next, this thesis proposes a novel adaptive pipelined MPSoC architecture, whereidle processors are transitioned into low-power states at run-time to reduce energyconsumption. Two run-time managers are proposed for the adaptive pipelined MPSoC.Firstly, a run-time processor manager is proposed to manage the idle processorsby either clock-gating or power-gating them. Secondly, a run-time power manageris proposed to select the most beneficial low-power state for an idle processor. Experimentswith an H.264 video encoder, designed for HD720p at 30 fps, showed thatthe processor manager provided an energy reduction of up to 34% and 39% whenclock-gating and power-gating was used respectively with a minimum throughputof 28.75 fps (which is within the specifications), compared to a pipelined MPSoCwithout run-time adaptability. Compared to the use of only the processor manager,the power manager reduced up to a further 40% energy consumption with only anadditional 0.5% degradation of the throughput.Lastly, this thesis proposes multi-mode pipelined MPSoCs, where multiple pipelinedMPSoCs designed separately are merged into a single pipelined MPSoC with modes.A multi-mode pipelined MPSoC enables further reduction of the area footprint bysharing the processors and FIFO buffers. Three merging heuristics are proposed tofind the maximal overlap between the individual pipelined MPSoCs, where the optimalityof the heuristics is traded-off with their running times. The results indicatedsignificant area footprint reduction – up to 62% processor area, 57% FIFO area and59% processor/FIFO ports – when compared to individual pipelined MPSoCs