Towards three dimensional all-epitaxial silicon architectures patterned by scanning tunnelling microscopy

This thesis develops a process to realise precise three dimensional architectures for silicon nanoelectronics, patterned by a scanning tunneling microscope (STM). In particular we combine ultra-high vacuum STM-lithography with gaseous phosphine doping and low temperature epitaxial silicon growth to realise vertically offset STMpatterned device layers for the purpose of gating one layer with another.We systematically optimised the formation of each &#0948 -layer component of a stacked device structure. We first demonstrated a maximum carrier density of 2.4×1014cm−2 in single Si:P δ -layers, 20% higher than previously reported. Low growth and incorporation anneal temperatures were required to minimise dopant segregation and prevent P desorption from the surface. We also found that by employing a interrupted double dosing technique we could prevent the formation of dopant precipitates to increase the planar carrier density to 3.6×1014cm−2.For vertically separated δ -layers we found that the activation of subsequent dopant layers was critically impacted by the surface crystallinity of the first encapsulated layer. We thus achieved full activation of Si:P bilayers measuring, 4.4×1014cm−2. For trilayer samples however, the maximum carrier density was limited at 4.3×1014cm−2 by a combination of reduced epitaxial quality, P segregation and deactivating donor pairs.Using the optimised bilayer recipe we then developed a multi-layer STM-patterned fabrication scheme to pattern an epitaxial top-gate above a STM-patterned nanowire. In an initial crossed wire architecture we demonstrated independent electrical contact to nanowires, vertically separated by 45 nm of epitaxial silicon. At 4.2K, the vertical tunnelling resistance between the nanowires was ∼ 167 M &#0937, much larger than the fourterminal resistance 80 k &#0937 of the 30 nm wide nanowire patterned on the low temperature overgrown silicon, and is consistent with previous STM-patterned wires in the literature. By increasing the silicon separation between STM-patterned layers to 120 nm we were able to produce a gating range of 2.6 V, sufficient to demonstrate conduction modulation in another STM-patterned device layer, demonstrating that low temperature grown epitaxial Si can be used as an effective gate dielectric. Finally we used a 100 nm wide Si:P doped top gate to observe stable and reproducible multi-island Coulomb blockade at cryogenic temperatures, in a 3 nm wide phosphorus doped silicon nanowire.These results demonstrate the viability of highly doped, vertically separated epitaxial gates in an all crystalline transistor architecture which show promise for the long-term realisation of monolithic epitaxial silicon circuits and scalable architectures for quantum computing