Design & Simulation of Second Stage & Three Stage OP-AMP Using 0.35µm CMOS Technology

A method is presented in this paper for the design of high speed CMOS Operational Amplifiers (Op-Amp).This paper is to design a Second Stage and Three Stage CMOS Operational amplifier and analyze the results of various aspect ratios on the characteristics of this Op-Amp, which operates at 3V to 5V power supply using TSMC 0.35pm CMOS technology. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18u M CMOS process. The design includes folded cascade op-amp with a unity gain frequency of 200MHz at 88° deg. The complete design topology of high gain-high bandwidth Op-Amp is presented between all characteristics such as Gain, Phase margin, CMRR etc. It also comprehensive improvements are seen in case of CMRR, PSRR, Offset Voltage and Transient performance at the expense of power and output resistance. Besides, for low power-low bandwidth application an optimum noise performance is achieved in this design. A Second stage Op-Amp the DC gain of the amplifier is 70 dB. The unity gain frequency and phase margin of the amplifier are 65 GHz and 43° and total power consumption of the Op-Amp is 0.070 mw. A Three stage OP-AMP the DC gain of the amplifier is 69 dB. The unity gain frequency and phase margin of the amplifier are 74 GHz and 43.5° and total power consumption of the Op- Amp is 0.062 mw. for a parallel combination of 2 pF and 1 kO load. I used AWR (microwave office) software for implement this work