Design & Simulation of Analog Phase Lock Loop With Ring oscillators Using 0.18µm CMOS Technology

This brief discusses the challenges and present techniques in designing analog phase-locked loops in nanometer CMOS. Phase Locked Loops are used in every communication system. Some of its uses include recovering clock from digital data signals, performing frequency, phase modulation and demodulation, recovering the carrier from satellite transmission signals and as a frequency synthesizer. There are many designs in communication that require frequency synthesizer to generate a range of frequencies; such as cordless telephones, mobile radios and other wireless products. The accuracy of the required frequencies is very important in these designs as the performance is based on this parameter. One approach to this necessity could be to use crystal oscillators. It is not only impractical, but is impossible to use an array of crystal oscillators for multiple frequencies. Therefore some other techniques must be used to circumvent the problem. The main benefit of using Phase Locked Loop technique in frequency synthesizers that it can generate frequencies comparable to the accuracy of a crystal oscillator and offer other advantages mentioned previously. For this reason most of the communication design make use of a PLL frequency synthesizer. Considering the scope of this single circuit, Phase locked loop is an excellent research topic as it covers many disciplines of electrical engineering such as Communication Theory, Control Theory, Signal Analysis, Noise Characterization, design with transistors and op-Amps, Digital Circuit design and non-linear circuit analysis. I am using .35µm CMOS Technology. I am using microwave office tools (AWR) to implement this work