Comparison Elements on STG DICE cell for Content-Addressable Memory and Simulation of Single-Event Transients

Comparison elements on base the STG DICE cell and the logical element “Exclusive OR” for a content-addressable memory were designed and simulated. The comparison element contains two identical joint groups of transistors that are spaced on the chip by the distance of four micrometers, so the loss of data in STG DICE cell practically excluded. On the characteristics of the new 65-nm CMOS comparison element, we predict the hardness of these item to single event rate (SER) more to hundred times compared to elements on 6-transistors cells and the standard DICE cell with distances 0.5-0.6 μm between mutually sensitive nodes