Nanoimprint lithography process optimization for the fabrication of high electron mobility transistors

We previously reported a procedure for the fabrication of high electron mobility transistors (HEMTs) using nanoimprint lithography [Y. Chen et al., Microelectron. Eng. 67,68, 189 (2003)] to produce T-shaped gates with 120 nm foot widths. The most recent batch of transistors fabricated by this original procedure had a peak transconductance of 450 mS/mm and f T fT of 40 GHz. In this article we describe a number of refinements to the original process with the main aims to improve performance and yield of devices. The work had two parallel strands. The first involved the development of improved silicon stamping tools to limit resist trenching effects and to produce stamping tools with smaller foot widths. T-shaped tools with 50 nm foot widths were produced from this work. The second strand of work was to optimize various aspects of transistor design and the imprint conditions used to fabricate gates which resulted in pHEMTs pHEMTs with a peak transconductance of 480 mS/mm and an f T fT of 75 Gh