Impact of process variations and technology scaling on synchronizer performance

Technology scaling has paved way for complex systems such as heterogeneous multi core processors, complex systems-on-a-chip (SoCs), etc with many multiple clock domains. Clock domain crossing (CDC) is an important issue that need to be addressed, as signals crossing clock-domains can lead to failures due to metastability. Thus, synchronizer designs are crucial in high performance systems. Typically, an n-stage synchronizer is used for synchronization, which needs n-cycle clock latency for synchronization. While this is a simple solution, it throttles the overall system performance. In this thesis, we have analysed three different synchronizer circuits for their synchronization behaviors. It is known that the mean time between failures (MTBF) has an exponential dependency on metastability constant ( ) of a synchronizer. Hence, a synchronizer with lower value of has very high MTBF. We have analysed three different synchronizer - standard D flip-flop, pseudo-NMOS synchronizer and dual-interlocked storage cell (DICE) flip-flop, in this work. It is known that the propagation delay of an inverter typically scales with technology. However, it is reported in an earlier work that this may or may not be so with metastability constant . Also, the effect of process variations on have not been studied in detail in the earlier works. It is also not clear how parasitic capacitances and resistances affect the value of , and whether it is essential to obtain after making the layout of every design. In this thesis we have made an attempt to provide answers and solutions to all these questions. The simulation for obtaining metastability has been performed in Cadence Virtuoso for planar devices and Hspice for FinFET devices. The statistical approach is used to vary the data near the edge of clock. Hence simulator options play an important role in finding metastability. The effect of technology scaling on metastability constant and propagation delay is being observed from 180nm to 28nm in CMOS planar devices using UMC process and 20nm to 7nm in non-planar FinFET devices using predictive technology models (PTM). The effect of process variations has been observed from 180nm to 28nm using UMC process for all the process corners. The impact of both process variations and technology node has been observed in three different kinds of flip-flops i.e. standard flip-flop (a standard cell D flip-flop), pseudo-NMOS flip-flop (a metastable hardened flip-flop) and DICE flip-flop (an SEU tolerant flip-flop). We show that pseudo-NMOS has the least among these three flip-flops and it's decreases with technology node and has also low process variations, but the propagation delay of pseudo-NMOS flop-flop is very high than other flip-flops. We also show that even though DICE flip is a radiation hardened flip-flop, it can also be used as a metastable hardened synchronizer because it has it's value very close to pseudo-NMOS flip-flop. It's process variations with parasitic have also been observed lowest in DICE flip-flop (5%). DICE flip-flop shows less with lowest propagation delay which benefits in term of metastability delay product (MDP)and metastability power delay product (MPDP).by Neha KumariM.Tech