Experimental investigation of DC-link capacitor voltage balancing in neutral point clamped inverter

"Demand to increase the efficiency and productivity, causes increase in the power rating of the machines. With increase in power rating, the power handling capability of the converters is also increased. One way to increase the power handling capability of the converters is by using the concept of multilevel. Neutral point clamped inverter is mostly used 3 level inverter in the industry for high power applications. The problem of DC-link voltage balancing between the capacitors is one of the major concern of this inverter. The unbalanced voltages of capacitors causes unbalanced levels in the output voltages. This unbalanced output levels in the voltages increases the harmonic content, which in turn cause heating losses in the machines. Many papers have been published in this area from last decade and most of these papers uses modulation technique to solve this problem. In this thesis Space Vector Modulation (SVM) technique is presented and it is shown that with the proper selection of switching states this problem can be mitigated. For nearest vector selection in SVM there are basically two techniques present in literature namely Nearest Three Vector (NTV) and Symmetric Modulation Technique (SYM). NTV technique uses proper selection of one Small vector per switching cycle. The balancing results are demonstrated in simulation and veri ed experimentally. NTV technique produces variable switching frequency, this causes unequal loss distribution and sometimes premature failure of switching devices. This problem of variable switching frequency is solved by using SYM technique. In this, both the dominant Small vector are used per switching cycle. The dwell time of the dominant Small vector is shared between its redundant states. In the literature, mathematical calculation for obtaining the proper dwell time share is not mentioned. Proper sharing of dwell time is very important since it results in effective DC-link voltage control across the capacitors. In this thesis, mathematical relation for calculating share dwell time for the redundant small vector states is proposed. It is shown that for effective balancing the share dwell time depends on phase currents and DC-link capacitor voltages. The derived calculations are veri ed in a real time simulator and later they are also tested by hardware in loop. A comprehensive comparison is also done to analyze the effect of these modulation techniques for DC-link capacitor balancing and the quality of output waveform they produce."by Mohit, ChandM.Tech