Aggressive technology scaling enables the implementation of multicore SoCs (Systems on Chip) for achieving better performance, but it also poses a great challenge due to various bottlenecks varying from architecture level, design level, gate level to interconnect level. This thesis evaluates the scaling effects on two issues- Global Interconnect Delay issue and Metastability issue during Synchronization. The critical paths of a chip are made of global interconnects which impact the chip performance. These critical paths need to be identified and their delays need to be optimized ahead of the HLD (High Level Design Phase) for the fastest timing closure. This puts the EDA (Electronic Design Automation) community in a challenging scenario as ...
As the core count in processor chips grows, so do the on-die, shared resources such as on-chip commu...
Multiple clock domains is one solution to the increasing problem of propagating the clock signal acr...
As semiconductor technology scales down, process variations become increasingly difficult to control...
Synchronizers are used at the clock domain crossings and at asynchronous interfaces to reduce the pr...
Technology scaling has paved way for complex systems such as heterogeneous multi core processors, co...
Synchronization is today among the most critical challenges in the design of a global on-chip commun...
Journal ArticleAs clock frequency increases and feature size decreases, clock distribution and wire...
As process nodes continue to shrink to improve transistor density and performance, it is causing an ...
In this paper, we use circuit simulations to characterize the effects of technology scaling on the m...
System on chip design steadily evolves toward different non-overlapping abstraction levels. Very di...
Abstract — Synchronizers play a key role in multi-clock domains systems on chip and their performanc...
Integrated systems with billions of transistors on a single chip are a now reality. These systems in...
With the rapid developments in VLSI technology, design, and CAD techniques, at both the chip and pac...
Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance ...
[[abstract]]Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI inter...
As the core count in processor chips grows, so do the on-die, shared resources such as on-chip commu...
Multiple clock domains is one solution to the increasing problem of propagating the clock signal acr...
As semiconductor technology scales down, process variations become increasingly difficult to control...
Synchronizers are used at the clock domain crossings and at asynchronous interfaces to reduce the pr...
Technology scaling has paved way for complex systems such as heterogeneous multi core processors, co...
Synchronization is today among the most critical challenges in the design of a global on-chip commun...
Journal ArticleAs clock frequency increases and feature size decreases, clock distribution and wire...
As process nodes continue to shrink to improve transistor density and performance, it is causing an ...
In this paper, we use circuit simulations to characterize the effects of technology scaling on the m...
System on chip design steadily evolves toward different non-overlapping abstraction levels. Very di...
Abstract — Synchronizers play a key role in multi-clock domains systems on chip and their performanc...
Integrated systems with billions of transistors on a single chip are a now reality. These systems in...
With the rapid developments in VLSI technology, design, and CAD techniques, at both the chip and pac...
Global interconnect is commonly regarded as a key potential bottleneck to the advancing performance ...
[[abstract]]Looks at the materials and thermal alternatives for scaled, next-century VLSI/ULSI inter...
As the core count in processor chips grows, so do the on-die, shared resources such as on-chip commu...
Multiple clock domains is one solution to the increasing problem of propagating the clock signal acr...
As semiconductor technology scales down, process variations become increasingly difficult to control...