A 5 GHz Ring-Oscillator PLL with Delay-Discriminator based Active Phase Noise Cancellation Loop

In this thesis phase locked loops are the building blocks of a communication system. So designing the PLL integrated circuit for communications applications is a great task. The PLLs utilizes VCOs for frequency generation and this is the critical block in PLLs. Ring oscillator (RO) based VCOs are better for the digital circuit applications as they are easy to integrate with in a small die area with the low cost. But these are very sensitive to supply noise these are having a limited-applications in the field of wireless communications. The other type of VCOs are LC tank VCOs the phase noise for this VCOs is very less but the tuning range here is not as good when compared to the RO VCOs. The tuning range can be improved by bulky passive resonators and often calibration architectures. Here we follow a approach of cancelling the phase noise with the active phase noise cancellation loop. The method used is delay discrimination method. The cancellation loop is designed to suppress the phase noise at 1-MHz. The phase noise in PLL without the cancellation loop is -72 dBc/Hz. The phase noise of PLL when active phase noise loop considered is -109 dBc/Hz. The proposed PLL with active phase noise cancellation loop is done in 180-nm CMOS technology. The PLL consumes 691.4 micro Ampere at 1.8-V suppl