Performance predictions for a silicon velocity modulation transistor.

A Monte Carlo simulation has been devised and used to model submicron Si velocity modulation transistors with the intention of designing a picosecond switch. The simulated devices have nominal top and back gate lengths of 0.1 μm, and the conduction channels have similar thickness. Mobility modulation has so far been achieved by heavily compensated doping and interface roughness at one side of the channel. The simulated devices have a high intrinsic speed; simulations performed for T = 77 K suggest that current can be switched between the low and high mobility regions of the channel within 1.5 ps. However, in unstrained Si devices the main obstacle to practical device operation is the rather small current modulation factor (the ratio of the steady drain currents for the device operating in the high and low mobility regimes), which decreases towards unity with increasing drain–source bias. Such a device should work best for small electric fields along the channel ( ∼ 105 V m−1), the regime where impurity scattering has its greatest influence on the electron mobility