Add to ORKGThis paper presents a radiation tolerant Phase-Locked Loop CMOS ASIC with an optimized Voltage Controlled Oscillator for Single-Event Upsets. The circuit has been experimentally verified with heavy ions and two-photon laser tests.status: publishe
The goal of this research was to develop and test integrated CMOS circuits for radiation tolerant ti...
Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. Hig...
The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for a...
This paper presents a radiation tolerant Phase-Locked Loop CMOS ASIC with an optimized Voltage Contr...
This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated cir...
This article presents the design of an LC-Tank voltage-controlled oscillator (VCO) for space and hig...
This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and h...
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL...
This paper presents experimental results for a CMOS ASIC with a ring- and LC-oscillator PLL that is ...
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for hig...
© 2019 IEEE. A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is pres...
High speed serial data communication links are required in most of today’s high-demanding systems. C...
Abstract — With decreasing feature sizes, lowered supply voltages and increasing operating frequenci...
Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices ...
Graduation date: 2006Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic...
The goal of this research was to develop and test integrated CMOS circuits for radiation tolerant ti...
Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. Hig...
The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for a...
This paper presents a radiation tolerant Phase-Locked Loop CMOS ASIC with an optimized Voltage Contr...
This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated cir...
This article presents the design of an LC-Tank voltage-controlled oscillator (VCO) for space and hig...
This work presents an introduction to radiation hardened Phase Locked Loops (PLLs) for nuclear and h...
This works presents the design and experimental study of a radiation hardened Phase Locked Loop (PLL...
This paper presents experimental results for a CMOS ASIC with a ring- and LC-oscillator PLL that is ...
A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is presented for hig...
© 2019 IEEE. A fault tolerant, radiation hardened Clock and Data Recovery (CDR) architecture is pres...
High speed serial data communication links are required in most of today’s high-demanding systems. C...
Abstract — With decreasing feature sizes, lowered supply voltages and increasing operating frequenci...
Phase-locked loop (PLL) systems are widely employed in integrated circuits for space analog devices ...
Graduation date: 2006Circuits operating outside the earth’s atmosphere are more vulnerable to cosmic...
The goal of this research was to develop and test integrated CMOS circuits for radiation tolerant ti...
Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. Hig...
The design and measurements results of a prototype very low power Phase-Locked Loop (PLL) ASIC for a...