Impact of the design layout on threshold voltage in SiGe channel UTBB-FDSOI pMOSFET
- Berthelon, Rémy
- Andrieu, F.
- Ortolland, S.
- Nicolas, R.
- Poiroux, T.
- Baylac, E.
- Dutartre, D.
- Josse, E.
- Claverie, Alain
- Haond, M.
Publication date
January 2016
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
cited By 3International audienceThe introduction of SiGe channel for pMOSFETs in FDSOI technology enables to achieve high performance. However, it has been demonstrated that such a global stressor induces layouts effects. In this paper, we present an exhaustive study of layout impact on threshold voltage. Especially, dissymmetric layouts, non-rectangular active areas and multifinger transistors are investigated. We propose an analytical model based on stress profile to reproduce the layout dependences. This model reproduces the experimental data with good accuracy, whatever the shape of the active area. © 2016 IEEE
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