An Ultracompact 9.4–14.8-GHz Transformer-Based Fractional-N All-Digital PLL in 40-nm CMOS

In this paper, we apply various area reduction techniques on an inductor–capacitor (LC)-tank oscillator in order to make its size comparable to that of ring oscillators (ROs), while still retaining its salient features of excellent phase noise and low sensitivity to supply variations. The resulting oscillator employs a proposed ultracompact split transformer topology that provides a 1:2 passive voltage gain and is less susceptible to common-mode electromagnetic interference than are regular high-quality-factor LC tanks, thus making it desirable in systemon-a-chip environments. The oscillator, together with a proposed dc-coupled buffer, is incorporated within an all-digital phaselocked loop (ADPLL) intended for wireline, digital clocking, and less stringent wireless systems. The ADPLL architecture introduces a look-ahead time-to-digital converter that exploits a deterministic phase prediction to reduce power consumption and phase detection complexity. The ADPLL is realized in 40-nm CMOS and has the smallest reported area of 0.0625 mm2 among LC-tank oscillators while providing fractional-N operation, wide tuning range of 45% (from 9.4 to 14.8 GHz), very low voltage supply sensitivity of 80 MHz/V, and integrated figure-of-merit jitter (FoMjitter) better than −230 dB. A separate identical ADPLL was implemented using an RO instead, for completeness and systematic comparisons