Add to ORKGIntegration of dielectrics with increased porosity is required to reduce the capacitance of interconnects. However, the conventional dual damascene integration approach is causing negative effects to these materials avoiding their immediate implementation. A post-CMP curing approach could solve some of these issues. However, materials with porogens being stable at temperatures of the barrier-seed deposition process are not common, hindering this approach. Here, we report on an extended dual-damascene integration approach which permits post-CMP curing
The drive for greater integrated circuit performance has led to the need for faster interconnect sys...
Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects....
textAs IC devices continue to shrink, the interconnect delay dominates over the gate delay in the c...
Integration of dielectrics with increased porosity is required to reduce the capacitance of intercon...
© 2015 AIP Publishing LLC. Cu/low-k integration by conventional damascene approach is becoming incre...
This paper reports about examinations on mechanical integrity improvement which were done to enable ...
Dielectric stacks containing porous low-k materials were investigated regarding their ability to pas...
© 2015 IEEE. Replacement of sacrificial template by ultralow-k dielectric was studied as an alternat...
Since the application of silicon materials in electronic devices in the 1950s, microprocessors are c...
A solid-first scheme was employed for making ultra low-k materials (k < 2.5) based on methylsilse...
Resistance-capacitance delay, crosstalk, and power dissipation associated with the increasing capaci...
In order to realize the high performance of RC delay, direct polished porous type ultra low-K film (...
Much effort has been undertaken to develop high performance ultra-low k ( ≤ 2.2) (ULK) dielectrics t...
Downlooften silicon nitride or silicon oxide, has a higher dielectric constant (high-k, 4.0 < k &...
An alternative indirect integration regime of porous low-k materials was investigated. Based on a si...
The drive for greater integrated circuit performance has led to the need for faster interconnect sys...
Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects....
textAs IC devices continue to shrink, the interconnect delay dominates over the gate delay in the c...
Integration of dielectrics with increased porosity is required to reduce the capacitance of intercon...
© 2015 AIP Publishing LLC. Cu/low-k integration by conventional damascene approach is becoming incre...
This paper reports about examinations on mechanical integrity improvement which were done to enable ...
Dielectric stacks containing porous low-k materials were investigated regarding their ability to pas...
© 2015 IEEE. Replacement of sacrificial template by ultralow-k dielectric was studied as an alternat...
Since the application of silicon materials in electronic devices in the 1950s, microprocessors are c...
A solid-first scheme was employed for making ultra low-k materials (k < 2.5) based on methylsilse...
Resistance-capacitance delay, crosstalk, and power dissipation associated with the increasing capaci...
In order to realize the high performance of RC delay, direct polished porous type ultra low-K film (...
Much effort has been undertaken to develop high performance ultra-low k ( ≤ 2.2) (ULK) dielectrics t...
Downlooften silicon nitride or silicon oxide, has a higher dielectric constant (high-k, 4.0 < k &...
An alternative indirect integration regime of porous low-k materials was investigated. Based on a si...
The drive for greater integrated circuit performance has led to the need for faster interconnect sys...
Plasma induced damage of ultra low-k (ULK) dielectrics is a common phenomenon in BEOL interconnects....
textAs IC devices continue to shrink, the interconnect delay dominates over the gate delay in the c...