Speed Efficient Hardware Implementation Of Advanced Encryption Standard (Aes)

Cryptography plays a vital role in data security against the attacks from the third party. In this thesis, the focus is to leverage existing, commonly used cryptography algorithm which is the Advanced Encryption Standard (AES) and improve its speed performance. The motivation is to make encryption process as short as possible to aid in increasing a system's ability to process large amount of data. FPGA is chosen as the platform due to it does not have software overhead and is meant to be customized for real time applications. Most of the researches are done on the area of optimizing hardware resources to implement AES on FPGA. The methods of optimization include on the fly computations and looping architecture, where all these of methods reduce the speed. This thesis presents a high throughput design of the 128-bit AES algorithm using loop unrolling, pipelined architecture and LUT approach which is able to work in parallel to allow accurate synchronization in order to fulfill the real time application needs. The system design is coded using Verilog HDL in ModelSim and the hardware design is analyzed through Altera Cyclone II in Quartus II. The maximum throughput of 32 Gbits/s operating at 250 MHz for the encryption process can be achieved. Also, one full cycle of a 128-bit AES encryption only needs 41 clock cycles in order to get the encrypted data. The comparison with the related works is done and eventually achieved higher throughput than the related works by 3.47% and 22% respectively. The two objectives set in this thesis are achieved