Power Management Controller By Using Intel Max 10 Fpga

Currently, FPGA (Field Programmable Gate Array) is one of the choices that consider for digital system design compare to ASIC (Application-Specific Integrated Circuit). This is due to the flexibility of the FPGA to update design based on the application. Intel Stratix 10 FPGA is the FPGA from Intel Cooperation that required proper power sequencing to avoid damage on the devices. Besides power sequencing, Intel Stratix 10 FPGA required 200 us to 100 ms POR (Power On Reset) during power up sequence to avoid FPGA in reset state and require total power down sequence in 100 ms. There are a lot of power sequencing methods are implemented for FPGA such as discrete component, resistor divider rule, sequencing IC (Integrated Circuit), MCU (Microcontroller), CPLD (Complex Programmable Logic Device) and FPGA. All these approaches are used to control the power on and off for the voltage regulator through pin enable voltage regulator and standard interface such as SM (System Management) Bus and PM (Power Management) Bus. For this project, non-volatile Intel MAX 10 FPGA is used for power management controller. This FPGA include internal ADC (Analog to Digital Converter) and UFM (User Flash Memory) that is critical to design power management controller. Power management controller is running on NIOS II and Avalon-MM (Memory-Mapped) Bus is used to connect all the ADC, UFM, timer, UART (Universal Asynchronous Receiver/Transmitter), PWM (Pulse Width Modulation) and PM Bus. This project is to power up and power down the PM Bus compatible voltage regulator within the POR specification which is 200 us to 100 ms and achieve 100 ms power down for FPGA. There are a number of advantages using Intel MAX 10 FPGA such as built in ADC, UFM, flexibility of FPGA, and NIOS II soft processor