Memory System Design for Chip-Multiprocessors

The continued decrease in transistor size and the increasing delay of wires relative to transistor switching speeds led to the development of chip multiprocessors (CMPs). The introduction of CMPs presents new challenges and trade-offs to computer architects. In particular, architects must now balance the allocation of chip resources to each processor against the number of processors on a chip. This thesis deals with some of the implications this new kind of processors have regarding the memory system and proposes several new designs based on the resource constraints of CMPs. In addition, it includes contributions on simulation technique and workload characterization, which is used to guide the design of new processors and systems. The memory system is the key to performance in contemporary computer systems. This thesis targets multiple aspects of memory system performance. To conserve bandwidth, and thereby packaging costs, a fine-grained data fetching strategy is presented that exploits characteristics of runahead execution. Two cache organizations are proposed: The RASCAL cache organization, which target capacity misses through selective caching and the Elbow cache that targets conflict misses by extending a skewed cache with a relocation algorithm. Finally, to reduce complexity and cost when designing multi-chip systems, a new trap-based system architecture is described. When designing a new processor or memory system, simulations are used to compare design alternatives. It is therefore very important to simulate workloads that accurately reflect the future use of the system. This thesis includes the first architectural characterization studies of Java-based middleware, which is a workload that is an important design consideration for the next generation of processors and servers