Several methods have been proposed to model communication in systems with coherent caches, e.g. multi-cores, however they usually incur a large overhead on the application being analyzed. In this work we describe a low-overhead statistical communication model that is driven by a sparse sample of the memory accesses in the target application. Our model allows detection of hot-spots where coherence communication occurs between different threads in an application. Preliminary results suggest that we are able to detect most of the communication hot-spots in real applications with lower overhead than previously proposed models.Coder-mpUPMAR
In this thesis, a discrete Markov chain model for analyzing memory interference in multiprocessors, ...
Single chip multicore processors are now prevalent and processors with hundreds of cores are being p...
One difficulty of programming multicore processors is achieving performance that scales with the num...
The transition to multi-core architectures can be attributed mainly to fundamental limitations in cl...
In a multicore environment, inter-thread communication can provide valuable insights about applicat...
In today's multi-core systems, cache contention due to true and false sharing can cause unexpected a...
In this paper we present simulation algorithms that characterize the main sources of communication g...
If the trend of integrating more and more cores to a single die continues, general-purpose processor...
Analyzing parallel programs has become increasingly difficult due to the immense amount of informati...
This thesis answers the question whether a scheduler needs to take into account where communicating...
In this paper we describe a compiler framework which can identify communication patterns for MPIbase...
In this paper we describe a compiler framework which can identify communication patterns for MPI-bas...
Shared memory multiprocessors are considered among the easiest parallel computers to program. Howeve...
Abstract Communications overhead is one of the most important factors affecting per-fonnance in mess...
textThis dissertation explores techniques for reducing the costs of inter-processor communication i...
In this thesis, a discrete Markov chain model for analyzing memory interference in multiprocessors, ...
Single chip multicore processors are now prevalent and processors with hundreds of cores are being p...
One difficulty of programming multicore processors is achieving performance that scales with the num...
The transition to multi-core architectures can be attributed mainly to fundamental limitations in cl...
In a multicore environment, inter-thread communication can provide valuable insights about applicat...
In today's multi-core systems, cache contention due to true and false sharing can cause unexpected a...
In this paper we present simulation algorithms that characterize the main sources of communication g...
If the trend of integrating more and more cores to a single die continues, general-purpose processor...
Analyzing parallel programs has become increasingly difficult due to the immense amount of informati...
This thesis answers the question whether a scheduler needs to take into account where communicating...
In this paper we describe a compiler framework which can identify communication patterns for MPIbase...
In this paper we describe a compiler framework which can identify communication patterns for MPI-bas...
Shared memory multiprocessors are considered among the easiest parallel computers to program. Howeve...
Abstract Communications overhead is one of the most important factors affecting per-fonnance in mess...
textThis dissertation explores techniques for reducing the costs of inter-processor communication i...
In this thesis, a discrete Markov chain model for analyzing memory interference in multiprocessors, ...
Single chip multicore processors are now prevalent and processors with hundreds of cores are being p...
One difficulty of programming multicore processors is achieving performance that scales with the num...