Application Task and Data Placement in Embedded Multi-core NUMA Architectures : Optimization techniques for the Samsung 16-SRP

The evolution of microprocessors has lead to a situation where more memory is integrated closer to the computational cores. This has created architectures where memory latencies vary depending on the calling cores location. Such architectures are referred to as Non-Uniform Memory Access (NUMA) architectures. This adds further complexity to the already complex environment of developing parallel applications. In this paper I research effective task and data placement optimization techniques for a Samsung Multi-Processor System-on-Chip (MPSoC) prototype. The research was structured by first conducting a series of extreme case micro benchmarks to gain insight of hardware behavior. These insights was then used to optimize two applications from the imaging domain; a 2D image blurring application and a 3D Seeded Region Growing (SRG) application. The results from conducted benchmarks show that a wide range of factors are of importance when optimizing applications for the Samsung 16-SRP architec- ture. Although NUMA penalties exists, reducing congestion at the memory controllers and in the DMA channels are of importance to overall execution time. I propose task and data distribution schemes that work well for benchmarks with static and dynamic workloads. Clustered hierarchical work queues with work stealing have shown to be an effective approach to optimizing applications with a dynamic workload. For future research it would be interesting to run further micro benchmarks of the system under congestion. To gain further verification of suggested task and data distribution schemes suggested in this thesis it would be of interest to apply them to more applications