High Level Synthesis of FPGA-Based Digital Filters

This thesis work is aimed at the high level synthesis of FPGA based IIR digital filters using Vivado HLS produced by Xilinx and HDL coder produced by MathWorks. The Higher Layer Model of the filter was designed in Vivado HLS, MATLAB and Simulink. Simulations, verification and Synthesis of the RTL code was done for both tools. Further optimizations were done so that the final design could meet the area, timing and throughput requirements. The resulting designs were later evaluated to see which of them satisfies the design objectives specified. This thesis work has revealed that Vivado HLS is able to generate more efficient designs than the HDL coder. Vivado provides the designer with more granularity to control scheduling and binding, the two processes at the heart of HLS. In addition, both tools provide the designer with transparency from modeling up to verification of the RTL code. HDL coder did not meet timing. Vivado HLS on the other hand met the timing requirements. The limitations of each design flow are also discussed in this report. A review of the tools available on the market today was also done and recommendations about them made. Finally, this thesis work recommends that ABB HVDC should adopt the HLS methodology using Vivado in order to achieve accelerated development. More work should be done to evaluate the possibility of auto C/C++ code generation for RTL synthesis in Vivado. Lastly, an evaluation on the LabVIEW environment should be done as an alternative to the HLS methodology