A methodology for power-model generation in Out-Of-Order Processors

This thesis presents a methodology to develop a power model for an Out-of-Order processor. The model is based on an existing simplistic power model and can estimate the power consumption of an application with better accuracy. To develop this model, a set of benchmarks are written, which have fine-grained instruction level events from an application as input. The benchmarks isolate the effect of these events on the power consumption of the processor and produce a data set that relates power and the events as output. Then, linear regression is used to establish the trend from the data sets and build the power model. A suite of real world applications is utilized to test the accuracy of this model. Comparison between the basic model and this newer model demonstrates its increased accuracy in estimating the power of a running application