Avalanche ISFET Sensing Chip for DNA Sequencing

DNA sequencing is a fundamental tool for biological science, aimed primarily at uncovering the genetic contributions to diseases. The first Human DNA sequence, which employed conventional fluorescent-based Sanger Sequencing method, took many years to complete at a cost of over three billion dollars. In one survey, it shows that Human Genome Project (HGP) had generated more than $67 billion in U.S. economic output, $20 billion in personal income for Americans and 310 thousand jobs in USA, only during year 2010. The HGP has increased the need for high-throughput, low cost, fast, accurate and inexpensive DNA sequence technique. This demand has forced a fundamental shift away from the conventional Sanger sequencing technique to Next Generation Sequencing (NGS) technique for genome analysis. NGS techniques provide high-throughput; low cost, user-friendly DNA sequencing and they are opening fascinating new opportunities in biomedicine. In near future, as the price of complete DNA sequencing goes further down to a few hundred dollars, we will then have DNA sequence data of millions of people. The enormous DNA sequencing data and corresponding correlation will allow us to figure out which sequences are responsible for which traits. As we relate the sequences of all of these people to their traits, we will be able to connect the dots and learn the genetic equations that define health, disease, longevity, intelligence, and other personality traits. In this dissertation, we propose a new avalanche ion-sensitive field effect transistor (A-ISFET) capable of sensing very weak pH changes during DNA synthesis. This is the first attempt to operate ISFET in avalanche mode. A-ISFET is the core of our proposed highly dense, low-cost and high-throughput DNA sequencing technique. To validate our proposed concept, we have designed, laid-out, fabricated, and successfully tested a test chip with arrays of A-ISFET using TSMC 0.25um CMOS process. Our research also includes the development of data processing circuits and system architectures for fast and efficient data processing. The test chip is used as the verification of this new DNA sequencing concept and the validation of the interfacial circuitry for the synchronization of sensing system. Each of the unit cells in the test chip is accessed through column-select and row-select signals during readout process. We design a test environment and test setup for correct readout of the sensing data from the chip through proper synchronizing signal. A specially milled and shaped structure is used to inlet and outlet the bio-chemical on the gate surface of the A-ISFET arrays. The inlet and outlet is attached to a time-controlled valve to control the flow of liquids on the surface of A-ISFET chip for test and verification of this novel DNA sensing concept. The test chip has been tested both at normal mode and at avalanche mode. Test results show that the sensitivity at avalanche mode is 6 times more than the normal mode of operation. We have developed a model to determine the signal-to-noise ratio (SNR) of A-ISFET. The model identifies that there is an optimum bias point of A-ISFET to have maximum SNR sensitivity from the sensor. Every electronic device generates its own intrinsic noise, in addition to other induced noise from associated nearby components. We have identified different noise components of A-ISFET and have modeled their respective characteristics with bias change. Different noise components that we find in A-ISFET are thermal noise, flicker noise, shot noise, and dark current noise. This noise modeling of A-ISFET sensor will help us to understand noise sources better and to predict the sensor behavior with change of bias. Using the noise model, we can select a bias point to minimize the noise impact of A-ISFET sensor and maximize its SNR. We also have developed a physical operation-based drain current model for A-ISFET during avalanche operation. Since A-ISFET operates in avalanche region, an accurate model for the breakdown behavior is therefore very important from both circuit design and circuit reliability point of view. The avalanche breakdown can result from impact ionization, a parasitic bipolar transistor, or the punch-through effect. Our developed model of A-ISFET drain current at avalanche region is due to impact ionization. We have validated the drain current model at avalanche through a correlation study among analytical model results, SPICE simulation results, and experimental measured results