FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures