Design Metrics for RTL level estimation of delay variability due to intradie (random) variations

A simple metric is presented for the accurate prediction of path delay variability within digital circuits synthesised from simple CMOS logic. This allows circuit variability to be assessed at early stages within the design process with minimal computational effort, as extensive Monte Carlo or SSTA runs are not required. This paper introduces the metric and investigates its effectiveness. The final predictions of path delay variability are found to be within 10% of measured path delay variability for a series of test paths synthesised from randomised models of a 130nm technology library. Future work will investigate the effectiveness of the metric for complex cell structures, and will analyse further technology nodes