System-level yield optimisation using hierarchical-based design flow

A new approach in hierarchical optimisation is presented, capable of optimising both the performance and yield of a system-level analogue circuit design. A behavioural model that combines the performance and variation from a Pareto-front is developed which can be used to optimise the system-level structure. The results have been verified with transistor-level simulations of a PLL and suggest that accurate performance and yield prediction can be achieved with the proposed design methodology