A new algorithm is presented that combines performance and variation objectives in a behavioural model for a given analogue circuit topology and process. The trade-offs between performance and yield are analysed using a combination of a multi-objective evolutionary algorithm and Monte Carlo simulation. The results indicate a significant improvement in overall simulation time and efficiency compared to conventional simulation based approaches, without a corresponding drop in accuracy. This approach is particularly useful in the hierarchical design of large and complex circuits where computational overheads are often prohibitive. The behavioural model has been developed in Verilog-A and tested extensively with practical designs using the Spec...
The synthesis of large digital integrated circuits is ubiquitous, highly developed, and efficient. D...
With the continuous downscaling of CMOS technology, precise control over process parameters has beco...
Continued process scaling has led to significant yield and reliability challenges for today’s design...
A new algorithm is presented that combines performance and variation objectives in a behavioural mod...
A new approach in hierarchical optimisation is presented which is capable of optimising both the per...
A novel technique is proposed in this paper that achieves a yield optimized design from a set of opt...
A new approach in hierarchical optimisation is presented, capable of optimising both the performance...
This paper describes an improved version of the program SEAS (a Simulated Evolution approach for Ana...
Monte-Carlo (MC) simulation is still the most commonly used technique for yield estimation of analog...
Semiconductor devices have rapidly improved in performance and function density over the past 25 yea...
This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up ...
As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances ...
Many methods for the statistical design and analysis of integrated circuits have been proposed over ...
As CMOS technologies move to sub-100nm regions, the design and verification for analog/mixed-signal ...
In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and res...
The synthesis of large digital integrated circuits is ubiquitous, highly developed, and efficient. D...
With the continuous downscaling of CMOS technology, precise control over process parameters has beco...
Continued process scaling has led to significant yield and reliability challenges for today’s design...
A new algorithm is presented that combines performance and variation objectives in a behavioural mod...
A new approach in hierarchical optimisation is presented which is capable of optimising both the per...
A novel technique is proposed in this paper that achieves a yield optimized design from a set of opt...
A new approach in hierarchical optimisation is presented, capable of optimising both the performance...
This paper describes an improved version of the program SEAS (a Simulated Evolution approach for Ana...
Monte-Carlo (MC) simulation is still the most commonly used technique for yield estimation of analog...
Semiconductor devices have rapidly improved in performance and function density over the past 25 yea...
This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up ...
As device dimensions continuously scale down in current MOS VLSI technology, statistical tolerances ...
Many methods for the statistical design and analysis of integrated circuits have been proposed over ...
As CMOS technologies move to sub-100nm regions, the design and verification for analog/mixed-signal ...
In nanometer complementary metal-oxide-semiconductor technologies, worst-case design methods and res...
The synthesis of large digital integrated circuits is ubiquitous, highly developed, and efficient. D...
With the continuous downscaling of CMOS technology, precise control over process parameters has beco...
Continued process scaling has led to significant yield and reliability challenges for today’s design...