MW²P-Bus: A New Bus Structure for Datapath Synthesis

Datapath optimisation has a great impact on the efficiency of computationally intensive embedded designs such as DSP blocks. Bus-oriented design is one of the low cost approaches to datapath synthesis but which suffers from a low data communication bandwidth %uniformly provided for all the connected units. It has been shown, on the other hand, that the word-length of functional units has a great impact on design costs. A combination of both methods is the core idea of this paper by offering an improved bus-oriented structure for datapath synthesis. In this method a datapath is partitioned into groups which are connected to a set of shared buses. Every bus segment has a different width and all the functional units connected to a bus segment have the same word-length. Having controlled the group binding and word-length of the functional units, as well as the other synthesis parameters, a high-level synthesis tool is introduced to implement DSP algorithms in register transfer level specification. The tool uses a multi-objective optimization algorithm to minimize the circuit area, delay, power consumption and digital noise by selecting optimal grouping and word-length for the bus structure. Results demonstrate that 25% to 75% savings can be made in the latency cost by applying this method