This paper proposes a frame work for High Level Synthesis of DSP algorithms with emphasis on differences between DSP systems and other digital systems. Accordingly a multiple word length has been used to optimize the system digital noise and area trade off. Based on a proposed architecture, required cost function, synthesiser and optimizer and intermediate data bases have been introduced and implemented. Optimization has been done by an optimizer based on Genetic Algorith
This paper presents an approach to the wordlength allocation and optimization problem for linear dig...
Abstract. When implementing software for programmable digital signal processors (PDSPs), the design ...
In this paper we propose a methodology that takes into account bit-width to optimize area and power ...
This paper proposes a frame work for High Level Synthesis of DSP algorithms with emphasis on differe...
This paper addresses the problem of choosing different word-lengths for each functional unit in fixe...
The word-length of Functional Units (FU) has a great impact on design costs. This paper addresses th...
International audienceField programmable gate arrays (FPGAs) are now considered as a real alternativ...
Field Programmable Gate Arrays (FPGAs) are now considered as a real alternative for Digital Signal P...
Abstract. Digital signal processing applications are implemented in embedded systems with fixed-poin...
Conventional approaches for fixed-point implementation of digital signal processing algorithms requi...
International audienceMultimedia applications such as video and image processing are often character...
Abstract—This project report presents a major update to the original word-length optimization tool f...
Abstract—A shared bus is a suitable structure for minimizing the interconnections costs in system sy...
International audienceDigital signal processing applications are implemented in embedded systems wit...
From high level synthesis point of view, target design can be divided into two parts: controller and...
This paper presents an approach to the wordlength allocation and optimization problem for linear dig...
Abstract. When implementing software for programmable digital signal processors (PDSPs), the design ...
In this paper we propose a methodology that takes into account bit-width to optimize area and power ...
This paper proposes a frame work for High Level Synthesis of DSP algorithms with emphasis on differe...
This paper addresses the problem of choosing different word-lengths for each functional unit in fixe...
The word-length of Functional Units (FU) has a great impact on design costs. This paper addresses th...
International audienceField programmable gate arrays (FPGAs) are now considered as a real alternativ...
Field Programmable Gate Arrays (FPGAs) are now considered as a real alternative for Digital Signal P...
Abstract. Digital signal processing applications are implemented in embedded systems with fixed-poin...
Conventional approaches for fixed-point implementation of digital signal processing algorithms requi...
International audienceMultimedia applications such as video and image processing are often character...
Abstract—This project report presents a major update to the original word-length optimization tool f...
Abstract—A shared bus is a suitable structure for minimizing the interconnections costs in system sy...
International audienceDigital signal processing applications are implemented in embedded systems wit...
From high level synthesis point of view, target design can be divided into two parts: controller and...
This paper presents an approach to the wordlength allocation and optimization problem for linear dig...
Abstract. When implementing software for programmable digital signal processors (PDSPs), the design ...
In this paper we propose a methodology that takes into account bit-width to optimize area and power ...