Multi-FPGA Synthesis with Asynchronous Communication Subsystems

With the ever-increasing complexity of digital designs, design abstraction has increased from schematic to language-based, and is migrating towards abstract behavioural specifications. Partitioning of the circuit or system into a collection of smaller, manageable components has become a central and critical design task. Asynchronous techniques of data synchronisation between partitioned designs, often in different clock domains, are well-researched areas in low power, and system on chip designs. In this paper, we present a high-level synthesis system that synthesises and generates structural outputs of a multi-FPGA system automatically without any modification of the source HDL code. The targeting of multiple prototyping boards trades off performance for improvement in prototyping time and cost. Optimised asynchronous communications channels with communications cells are inserted automatically to the multi-FPGA implementation during synthesis, synchronising inter-FPGA data packets transferred asynchronously between FPGAs in different clock domains