Add to ORKGThis work describes a high frequency dual modulus divider designed and fabricated in a 0.35/spl mu/m PDSOI process, employing a stacked topology phase switching scheme. SOI CMOS technology is exploited to allow current re-use in a higher supply voltage than dictated by single device breakdown. Measurements show the circuit operating at 3GHz (Vdd = 6.8V)
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
A stacked CMOS technology fabricated on semic conductor-on-insulator (SOI) wafers with the p-MOSFET ...
This paper describes modification of conventional CML gates as used in frequency dividers by replaci...
One of the key components common in integrated receiver designs is a RF local oscillator. This parti...
Abstruct- The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider...
The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presen...
A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescal...
Abstract Two mmWave frequency dividers were designed, manufactured and measured using static curren...
This paper describes a double polysilicon bipolar process incorporating a novel self-aligned emitter...
Abstract — A dual-modulus (divide-by-16/17) prescaler has been designed using a 0.35µm CMOS technolo...
In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presen...
A methodology to design high-speed power-efficient MOS Current-Mode Logic (MCML) static frequency di...
In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Cu...
Abstract A programmable dual modulus divider was proposed. The circuit mainly includes three buildin...
Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at u...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
A stacked CMOS technology fabricated on semic conductor-on-insulator (SOI) wafers with the p-MOSFET ...
This paper describes modification of conventional CML gates as used in frequency dividers by replaci...
One of the key components common in integrated receiver designs is a RF local oscillator. This parti...
Abstruct- The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider...
The architecture of a high-speed low-power-consumption CMOS dual-modulus frequency divider is presen...
A 64-modulus prescaler operating at 5.8 GHz has been designed in a 0.18 μm CMOS process. The prescal...
Abstract Two mmWave frequency dividers were designed, manufactured and measured using static curren...
This paper describes a double polysilicon bipolar process incorporating a novel self-aligned emitter...
Abstract — A dual-modulus (divide-by-16/17) prescaler has been designed using a 0.35µm CMOS technolo...
In this article, a static frequency divider based on folded MOS current mode logic (FMCML) is presen...
A methodology to design high-speed power-efficient MOS Current-Mode Logic (MCML) static frequency di...
In this paper a low-voltage, high speed frequency divider architecture exploiting the Folded MOS Cu...
Abstract A programmable dual modulus divider was proposed. The circuit mainly includes three buildin...
Two frequency divider architectures in the Folded MOS Current Mode Logic which allow to operate at u...
Abstract—In this paper we present the design of a pro-grammable frequency divider in 28 nm FD-SOI CM...
A stacked CMOS technology fabricated on semic conductor-on-insulator (SOI) wafers with the p-MOSFET ...
This paper describes modification of conventional CML gates as used in frequency dividers by replaci...