<p>Multiplexing parallel busses into serial links has been proposed for its advantages such as reducing inter connect area, coupling capacitance and crosstalk. But serialization increases bit transition which increases the activity switching factor and power dissipation. Many coding schemes have been proposed to optimize the activity switching factor which is a result of increased number of bit transitions. This paper compares some of the techniques which are used to reduce the activity switching factor and the power dissipation. This paper gives an overview of the bus invert coding, the weight based bus invert coding, the partial bus invert coding, the serialized low energy transmission coding, the transition inversion coding, and the embe...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the nois...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Low power VLSI circuit design is one of the most important issues in present day technology. One of ...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...
Abstruct- Technology trends and especially portable applications drive the quest for low-power VLSI ...
The selection of the right low-power coding technique during the design of the interconnect architec...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In this paper we propose a coding scheme for general-purpose applications that can reduce power diss...
The authors propose a partial bus-invert coding scheme that reduces the total number of bus transit...
Dynamic power dissipation on I/O buses is an important issue for high-speed communication between ch...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the nois...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...
Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Var...
Low power VLSI circuit design is one of the most important issues in present day technology. One of ...
We present a partial bus-invert coding scheme for power optimization of system level bus. In the pro...
A data-distribution and bus-structure aware methodology for the design of coding schemes for low-pow...
Abstract The energy dissipation associated with driving long wires accounts for a significant fracti...
Power dissipation is an important design constraint in today’s CMOS VLSI design and is addressed wid...
Abstruct- Technology trends and especially portable applications drive the quest for low-power VLSI ...
The selection of the right low-power coding technique during the design of the interconnect architec...
[[abstract]]In this paper, we propose a bus encoding scheme to minimize coupling effects which cause...
In this paper we propose a coding scheme for general-purpose applications that can reduce power diss...
The authors propose a partial bus-invert coding scheme that reduces the total number of bus transit...
Dynamic power dissipation on I/O buses is an important issue for high-speed communication between ch...
In this paper we present a simplified model for deep submicron, on-chip, parallel data buses. Using ...
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the nois...
This paper presents two bus coding schemes for power optimization of application-specific systems: ...