The vertical MOSFET structure is one of the solutions for reducing the channel length of devices under 50nm. Surround gate structures can be realised which offer improved short channel effects and more channel with per unit silicon area. In this paper, a low technology overlap capacitance, surround gate, vertical MOSFET technology is presented, which uses fillet local oxidation (FILOX) to reduce the overlap capacitance between the gate and the drain on the bottom of the pillar. Electrical characteristics of surround gate n-MOSFETs are presented and compared with results from single gate and double gate devices on the same wafer. The devices show good symmetry between the source on top and source on bottom configuration. The short channel ef...
The integration of high voltage power transistors with control circuitry to form smart Power Integra...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
We report for the first time a silicidation technology for surround gate vertical MOSFETs. The techn...
The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors...
The international technology roadmap for semiconductors predicts that downscaling of the dimensions ...
We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MO...
We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable f...
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transist...
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transist...
This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFET...
In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet loca...
We report simulations and experimental work relating to innovations in the area of ultra short chann...
Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to ...
Abstract-We present a review of recent reports on vertical MOSFETs which includes a summary of our o...
Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacit...
The integration of high voltage power transistors with control circuitry to form smart Power Integra...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
We report for the first time a silicidation technology for surround gate vertical MOSFETs. The techn...
The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors...
The international technology roadmap for semiconductors predicts that downscaling of the dimensions ...
We report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MO...
We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable f...
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transist...
Application of double gate or surround-gate vertical metal oxide semiconductor field effect transist...
This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFET...
In this work we investigate the series resistances in vertical MOSFETs incorporating the fillet loca...
We report simulations and experimental work relating to innovations in the area of ultra short chann...
Vertical Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is believed to ...
Abstract-We present a review of recent reports on vertical MOSFETs which includes a summary of our o...
Vertical MOSFETs (VMOSFETs) with channel lengths down to 100nm and reduced overlap parasitic capacit...
The integration of high voltage power transistors with control circuitry to form smart Power Integra...
This paper investigates the asymmetrical characteristics of junctions and their nearby regions in su...
We report for the first time a silicidation technology for surround gate vertical MOSFETs. The techn...