Code compression based on operand-factorization for VLIW processors

As programs become more complex for both embedded systems and large-scale applications, bloated code size continues to be an ever increasing problem. The size of object code greatly effects the space used and ultimately contributes greatly to cost. Code compression techniques have been devised as a way of battling large code. Code compression algorithms usually require specific techniques to maintain the integrity of the program and ensure its functionality. This paper presents three code compression algorithms based on dictionary methods for entire instructions, instructions factorized into op-code/operand pairs and operand factorization applied to instruction words. MediaBench benchmarks are compiled for maximum code optimization on the TI TMS320C6x then compressed. Compression Ratios (defined as the ratio of compressed code to uncompressed code) of 81.5%, 68.3% and 84.7% are reported for the three compression schemes. The instruction-based factorization scheme outperforms the other schemes in relation to code size, but requires sequential decompression of unit instructions. Operand factorization across instruction words allows for decompression of instructions in parallel at a cost to the compression ratio