Power semiconductor device

A power semiconductor device is described. The device comprises a silicon carbide substrate and a layer of monocrystalline silicon having a thickness no more than 5um disposed directly on the substrate or directly on an interfacial layer having a thickness no more than 100 nm which is disposed directly on the substrate. The device comprises a lateral transistor, such as a laterally-diffused metal oxide semiconductor (LDMOS) transistor or lateral insulated gate bipolar transistor (LIGBT), comprising first and second contacts laterally-spaced contact regions disposed in the monocrystalline silicon layer