Writing a RVM-Compliant AHB Master Transactor

The use of AMBA-based buses is ubiquitous in today’s System On Chips (SoC). Verification IPs (VIP) are effective in generating stimuli for block-level, subsystem-level, and top-level testbenches. The reference verification methodology (RVM) and its base class library for Vera help verification engineers to build a testbench that enables constrained random verification and promotes re-use. Keeping the transactors in an RVM style makes them have the same look and feel and consequently make them easier to use (e.g. when writing tests). This paper discusses how an RVM compliant AHB master transactor is designed using the DesignWare AHB Master VIP and demonstrates how to configure it for the testbench and how to create test stimuli using the transacto