The architecture of RIG: a RISC for image generation in a multi-microprocessor environment

RIG is a fast Reduced Instruction Set Processor suitable for Real-Time Image Generation (RTIG) Geometric Computations. It is designed to be used in a parallel processing architecture, so that high polygon throughput can be achieved. RIG is a 16 MIPS processor that can execute the geometric computations required in RTIG at least ten times faster than a MC68000-12Mhz microprocessor due to the following innovations and characteristics:• A novel “Data Ready” technique, in which data is available without waiting for external memory. Data is transferred in burst mode (via DMA) directly into processor internal registers in parallel with processing.• “Indices” to the General-Purpose Registers instead of “Register Windows” schemes, as a fast and efficient parameter passing mechanism in procedure calls.• Fast multiplication and division instructions together with a three-staged pipeline architecture with “data forwarding”.• Extremely fast interaction with a parallel processing system with minimum overhead